The Innovation Firm

Luke Demoracski, Ph.D.

Practice Areas

Technologies

Education

  • Worcester Polytechnic Institute, B.S. in Electrical Engineering, With Distinction
  • Northeastern University, M.S. in Electrical Engineering
  • Northeastern University, Ph.D. in Electrical Engineering
  • Suffolk University Law School, J.D. Expected May 2017

Professional Associations

  • IEEE Boston Entrepreneurs’ Network Member
  • IEEE Senior Member
  • Boston Patent Law Association
  • Tau Beta Pi, the National Engineering Honor Society
  • Eta Kappa Nu, the Electrical and Computer Engineering Honor Society
  • Phi Delta Phi Honorary Legal Fraternity

Luke Demoracski, Ph.D.

Luke Demoracski, Ph.D. Attorney

Luke Demoracski, Ph.D.

Patent Agent
Concord office
978.341.0036

Luke assists with patent preparation and prosecution in a variety of areas, with a particular emphasis in computer systems, electronics, software and telecommunications.

Luke has a wide range of industry experience that spans hardware and software technologies, including ASIC, FPGA, board and system design and verification, automated test equipment, computer systems, fault tolerance, wired and wireless networks, networking protocols, telecommunication systems, and several software and hardware languages.

Luke’s legal experience includes assisting in drafting patent applications for electrical and mechanical technologies, replies to Office actions, and infringement analyses.

Luke has over 15 years of industry experience as an electrical engineer at various companies.  His engineering roles have included technical leadership, design, quality testing and verification, both for hardware and software.  He served as a consultant to clients including Analog Devices, Cavium, Intel, Lucent Technologies, MIT Draper Labs, Nortel Networks, Qualcomm, and Teradyne.  Luke’s other experience includes work for Motorola Mobility developing networking products in the field of cable modem technology, General Dynamics developing electronics for Navy submarine programs, Teradyne developing automated test equipment, and the start-up Equipe Communications developing ATM/MPLS networking products.

At Northeastern University, Luke performed significant research in the areas of hardware and software co-design, EDA tools, fault-tolerance, wireless computer networking, nanotechnology, DNA self-assembly, and formal verification.  The title of his doctoral dissertation was Fault-Tolerant Routing for Wireless Multi-hop Networks.  He has co-authored 10 scientific publications and authored one.  He has served for the Institute of Electrical and Electronics Engineers (IEEE) as a manuscript reviewer and as local chair to the IEEE International Symposium on Network Computing and Applications.

Publications

  • A Scalable Framework for Defect Isolation of DNA Self-Assembled Networks, The 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, September 2007
  • Connecting and Configuring Defective Nano-Scale Networks for DNA Self-Assembly, First Annual IEEE Symposium on Nano-Networks, September 2006
  • Performance Analysis of Fault-Tolerant Beacon Vector Routing for Wireless Sensor Networks, ACM/IEEE International Symposium on Modeling, Analysis and Simulation of Wireless and Mobile Systems, October 2005
  • Topology Selection for Fault-Tolerant Beacon Vector Routing in Wireless Sensor Networks, IEEE International Conference on Networking and Services, October 2005
  • Correctness of Fault-Tolerant Cluster-Based Beacon Vector Routing for Ad Hoc Networks, IEEE International Conference on Wireless and Mobile Computing, Networking and Communications, August 2005
  • Cluster-based Load-Balanced Fault-Tolerant Beacon Vector Routing for Wireless Sensor Networks, IEEE Dependable Systems and Networks Conference, July 2005
  • An Approach Functional Decomposition Applied to State-Based Designs, IEEE Rapid System Prototyping Workshop, June 2005
  • Design Verification with 0-In Assertions: A Case Study, First Annual Teradyne Technical Conference, June 2005
  • Framework for Improved Partitioning and Automatic Task Graph Extraction for State-Based Designs, International Workshop on Logic Synthesis, June 2005
  • Fault-Tolerant Beacon Vector Routing for Mobile Ad Hoc Networks, IEEE International Parallel and Distributed Processing Symposium, April 2005
  • Power Consumption Comparison for Regular Wireless Topologies using Fault-Tolerant Beacon Vector Routing, IEEE International Parallel and Distributed Processing Symposium, April 2005

Bar Admissions

  • U.S. Patent and Trademark Office
Biography

Luke assists with patent preparation and prosecution in a variety of areas, with a particular emphasis in computer systems, electronics, software and telecommunications.

Luke has a wide range of industry experience that spans hardware and software technologies, including ASIC, FPGA, board and system design and verification, automated test equipment, computer systems, fault tolerance, wired and wireless networks, networking protocols, telecommunication systems, and several software and hardware languages.

Luke’s legal experience includes assisting in drafting patent applications for electrical and mechanical technologies, replies to Office actions, and infringement analyses.

Luke has over 15 years of industry experience as an electrical engineer at various companies.  His engineering roles have included technical leadership, design, quality testing and verification, both for hardware and software.  He served as a consultant to clients including Analog Devices, Cavium, Intel, Lucent Technologies, MIT Draper Labs, Nortel Networks, Qualcomm, and Teradyne.  Luke’s other experience includes work for Motorola Mobility developing networking products in the field of cable modem technology, General Dynamics developing electronics for Navy submarine programs, Teradyne developing automated test equipment, and the start-up Equipe Communications developing ATM/MPLS networking products.

At Northeastern University, Luke performed significant research in the areas of hardware and software co-design, EDA tools, fault-tolerance, wireless computer networking, nanotechnology, DNA self-assembly, and formal verification.  The title of his doctoral dissertation was Fault-Tolerant Routing for Wireless Multi-hop Networks.  He has co-authored 10 scientific publications and authored one.  He has served for the Institute of Electrical and Electronics Engineers (IEEE) as a manuscript reviewer and as local chair to the IEEE International Symposium on Network Computing and Applications.

Publications

  • A Scalable Framework for Defect Isolation of DNA Self-Assembled Networks, The 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, September 2007
  • Connecting and Configuring Defective Nano-Scale Networks for DNA Self-Assembly, First Annual IEEE Symposium on Nano-Networks, September 2006
  • Performance Analysis of Fault-Tolerant Beacon Vector Routing for Wireless Sensor Networks, ACM/IEEE International Symposium on Modeling, Analysis and Simulation of Wireless and Mobile Systems, October 2005
  • Topology Selection for Fault-Tolerant Beacon Vector Routing in Wireless Sensor Networks, IEEE International Conference on Networking and Services, October 2005
  • Correctness of Fault-Tolerant Cluster-Based Beacon Vector Routing for Ad Hoc Networks, IEEE International Conference on Wireless and Mobile Computing, Networking and Communications, August 2005
  • Cluster-based Load-Balanced Fault-Tolerant Beacon Vector Routing for Wireless Sensor Networks, IEEE Dependable Systems and Networks Conference, July 2005
  • An Approach Functional Decomposition Applied to State-Based Designs, IEEE Rapid System Prototyping Workshop, June 2005
  • Design Verification with 0-In Assertions: A Case Study, First Annual Teradyne Technical Conference, June 2005
  • Framework for Improved Partitioning and Automatic Task Graph Extraction for State-Based Designs, International Workshop on Logic Synthesis, June 2005
  • Fault-Tolerant Beacon Vector Routing for Mobile Ad Hoc Networks, IEEE International Parallel and Distributed Processing Symposium, April 2005
  • Power Consumption Comparison for Regular Wireless Topologies using Fault-Tolerant Beacon Vector Routing, IEEE International Parallel and Distributed Processing Symposium, April 2005
Education
  • Worcester Polytechnic Institute, B.S. in Electrical Engineering, With Distinction
  • Northeastern University, M.S. in Electrical Engineering
  • Northeastern University, Ph.D. in Electrical Engineering
  • Suffolk University Law School, J.D. Expected May 2017
Professional Associations
  • IEEE Boston Entrepreneurs’ Network Member
  • IEEE Senior Member
  • Boston Patent Law Association
  • Tau Beta Pi, the National Engineering Honor Society
  • Eta Kappa Nu, the Electrical and Computer Engineering Honor Society
  • Phi Delta Phi Honorary Legal Fraternity
Bar Admissions
  • U.S. Patent and Trademark Office

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