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Joe’s focus is in patent preparation and prosecution in the areas of electrical and computer engineering. Joe has over 11 years of industry experience as an electrical engineer in the semiconductor industry.

Prior to joining the firm, Joe was a test development engineer at Analog Devices. He was responsible for designing and debugging automated test environment (ATE) applications for various amplifier products, including op-amps, in-amps, and multi-amplifier ASICs, such as an analog front end for a wearable heart rate monitor. In addition to circuit, PCB, software, and mechanical aspects of ATE designs, Joe’s projects often required an optimized, on-chip, laser-trim resistor layout to achieve a specified resistance, range, and trim resolution.

While at Analog Devices, Joe extensively refined an existing algorithm for detecting electrical noise. The refined algorithm was applied to several products, and provided wafer-level noise data to fabrication engineers, facilitating their efforts to address root causes of noise issues at the transistor level. In conjunction with mentoring other test engineers on specialized wafer-level trim and probe equipment, Joe authored a tutorial to address the challenges associated with developing wafer-level probe applications on a final package-test manufacturing floor. 

Joe earned his Master’s of Science degree in electrical and computer engineering from Northeastern University and his Bachelor of Science degree in electrical engineering from the University of Connecticut (UConn). While at UConn, Joe performed PCB debug and provided frequency response data for a team working on a low-frequency photoacoustic medical imaging system.


  • B.S. in Electrical Engineering, University of Connecticut
  • M.S. in Electrical and Computer Engineering, Northeastern University